(1) Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a structure of a device isolation area in the semiconductor device.
(2) Description of the Related Art
Conventionally, if a semiconductor substrate is made of silicon (Si), the most widely used structure of the isolation area between the devices constituting a semiconductor device is a LOCOS (Local Oxidation of Silicon) structure. As shown in FIG. 1, this LOCOS structure comprises field oxide films formed by selectively oxidizing the surface of the silicon substrate. For example, with a P-type silicon substrate, the LOCOS structure is formed in such a way that boron (B) is selectively ion-implanted into the surface of the silicon substrate 401 to form channel stopper regions 404, and selective oxidation is performed to form silicon oxide films 405 having a thickness of 500 nm or so on the channel stopper regions 404.
With development of high integration and high density in semiconductor devices, a miniaturized structure has been required for the isolation area between devices or elements. In order to relax the lower limit of the size of the device isolation area due to the bird's beak of LOCOS or to prevent crystal defects from being produced, several LOCOS structures which are generally called modified LOCOSs have been proposed.
Further, new device isolation area structures which are more suitable for device miniaturization have been also proposed. Among them, particularly, a trench type device isolation area structure in which a trench or groove is formed on a semiconductor substrate surface has been researched. This technique is to form a trench on a semiconductor substrate, form insulating films on the side walls and fill the trench with insulating material.
It should be noted that the semiconductor device having the device isolation area structure as described above has the following problems.
With the LOCOS structure (or modified LOCOS structure), a semiconductor device comprising MOS transistors as shown in FIG. 2 are fabricated as follows. After the structure shown in FIG. 2 has been made, gate oxide films, gate electrodes 410, source/drain regions 411a, 411b and an interlayer film 412 are formed. After contact holes reaching the source/drain regions 411a, 411b have been opened, electrode wirings 413 and then a covering film 414 are formed. In the above process, the source/drain regions 411a and 411b and the device isolation areas 405 are formed so as to be substantially coplanar. Thus, the insulation withstand voltage between the source/drain regions 411a of the first MOS transistor and the source/drain regions 411b of the adjacent second MOS transistor abruptly lowers if the width of the isolation region 405 is not larger than 0.5 .mu.m. As a result, reducing the isolation area will be limited by this fact.
Further, in the case of the trench type isolation area, its size (width) can be reduced to 0.1 .mu.m or so by using the dry-etching technique. However, since a large difference in the thermal expansion coefficient is present between the insulating material filled in the trench and the semiconductor substrate, crystal defects will be likely to occur within the semiconductor substrate in the process of fabricating the semiconductor device.